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this document contains information on a product under development at advanced micro devices inc. the information is intended to help you to evaluate this product. amd reserves the right to change or discontinue work on this proposed product without notice. publication# 16506 rev. c amendment /0 issue date: may 1993 advanced micro devices am53c94/AM53C96 high performance scsi controller preliminary distinctive characteristics n pin/function compatible with ncr53c94/53c96 n amd's patented glitch eater tm circuitry on req and ack inputs n 5 mbytes per second synchronous scsi transfer rate n 20 mbytes per second dma transfer rate n 16-bit dma interface plus 2 bits of parity n flexible three bus architecture n single ended scsi bus supported by am53c94 n single ended and differential scsi bus supported by AM53C96 n selection of multiplexed or non-multiplexed address and data bus n high current drivers (48 ma) for direct connection to the single ended scsi bus n supports disconnect and reselect commands n supports burst mode dma operation with a threshold of 8 n supports 3-byte-tagged queuing as per the scsi-2 specification n supports group 2 and 5 command recognition as per the scsi-2 specification n advanced cmos process for low power consumption n am53c94 available in 84-pin plcc package n AM53C96 available in 100-pin pqfp package general description the high performance scsi controller (hpsc) has a flexible three bus architecture. the hpsc has a 16-bit dma interface, an 8 bit host data interface and an 8-bit scsi data interface. the hpsc is designed to minimize host intervention by implementing common scsi se- quences in hardware. an on-chip state machine re- duces protocol overheads by performing the required sequences in response to a single command from the host. selection, reselection, information transfer and disconnection commands are directly supported. the 16-byte-internal fifo further assists in minimizing host involvement. the fifo provides a temporary stor- age for all command, data, status and message bytes as they are transferred between the 16 bit host data bus and the 8 bit scsi data bus. during dma operations the fifo acts as a buffer to allow greater latency in the dma channel. this permits the dma channel to be sus- pended for higher priority operations such as dram re- fresh or reception of an isdn packet. parity on the dma bus is optional. parity can either be generated and checked or it can be simply passed through. the patented glitch eater circuitry in the high per- formance scsi controller detects signal changes that are less than or equal to 15 ns and filters them out. it is designed to dramatically increase system performance and reliability by detecting and filtering glitches that can cause system failure. the glitch eater circuitry is implemented on the ack and req lines only. these lines often encounter many electrical anomalies which degrade system per- formance and reliability. the two most common are re- flections and voltage spikes. reflections are a result of high current scsi signals that are mismatched by stubs, cables and terminators. these reflections vary from ap- plication to application and can trigger false handshake signals on the ack and req lines if the voltage ampli- tude is at the ttl threshold levels. spikes are generated by high current scsi signals switching concurrently. on the control signals ( ack and req ) they can trigger false data transfers which result in loss of data, addition of random data, double clocking and reduced system reli- ability. amds glitch eater circuitry helps maintain excellent system performance by treating the glitches. refer to the diagram on the next page.
p r e l i m i n a r y amd 2 am53c94/AM53C96 scsi environment valid signal glitches >15 ns < 15 ns glitches pass through as valid signals ack or req input device without the glitch eater circuit glitches filtered amds device with the glitch eater circuit valid signal passes 16506c-1 glitch eater circuitry in scsi environment ack or req input system block diagram 9 cpu dma memory am53c94/96 8 16 16 4 9 scsi data 16 dma addr data 16506c-2 scsi control 16
p r e l i m i n a r y amd 3 am53c94/AM53C96 system bus mode diagrams 16506c-3 8-bit data bus address bus dma controller host processor am53c94/96 bus controller dma 7C0 a 3C0 rd wr dmawr busmd 0 busmd 1 dreq dack bus mode 0 16506c-4 data bus address bus rd wr dmawr dreq dack dma controller host processor am53c94/96 bus controller dma 15C0 a 3C0 busmd 0 busmd 1 8 16 v dd bus mode 1
p r e l i m i n a r y amd 4 am53c94/AM53C96 system bus mode diagrams dmard v dd 8-bit data bus 16506c-5 dma controller host processor am53c94/96 dma 15C0 ad 7C0 wr dmawr busmd 0 busmd 1 dreq dack rd bhe as0 ale 16-bit data bus bus mode 2 v dd address bus 16506c-6 dma controller host processor am53c94/96 dma 15C0 a 3C0 wr dmawr busmd 0 busmd 1 dreq dack rd 16-bit data bus 8-bit data bus ad 7C0 bus mode 3
p r e l i m i n a r y amd 5 am53c94/AM53C96 block diagram 16506c-7 bus interface unit 18 18 16 x 9 fifo (including parity) parity logic data tranceivers scsi control mux 8 8 8 9 clk 6 4 dma 15-0 dmap 1-0 dma control ad 7-0 host control busmd 1-0 reset cs 9 scsi control scsi bus data + parity (single ended) main sequencer scsi sequencer register bank dfmode 9 scsi bus data + parity direction control 7 scsi control direction control
p r e l i m i n a r y amd 6 am53c94/AM53C96 connection diagrams top view 16506c-8 dma11 dma10 dma9 dma8 dma7 dma3 dma2 dma1 dma0 dma4 dmap0 dmap1 dma14 dma13 dma12 dma15 dma5 dma6 ad3 ad2 ad1 ad0 clk ale [a3] dmard [a2] bhe [a1] as0 [a0] ad4 ad5 dreq dack dmawr ad6 ad7 cs rd wr bsyc reqc msg c/d i/o atn rstc sel bsy req ack rst busmd 0 int reset selc busmd 1 ackc 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 74 73 72 71 70 69 68 67 66 65 64 63 62 61 59 58 57 56 55 54 60 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 111098765432184838281807978777675 am53c94 84-pin plcc sd 6 sd 7 sd p v dd vss v ss sd 3 sd 4 sd 5 sd 0 sd 1 sd 2 sdc 3 sdc 0 sdc 1 sdc 2 sdc 6 sdc 7 sdc p sdc 4 sdc 5 v dd v ss v ss v ss v ss v ss v ss v ss nc isel tsel dma0 dma1 dma2 dma3 dma4 dma5 dma6 dma7 dmap0 dma8 dma9 dma10 dma11 dma12 dma13 dma14 dma15 dmap1 nc sd 0 sd 1 dack dmawr nc sdc 7 sdc p busmd 0 busmd 1 rst ack req sel atn i/o c/d msg ackc reqc bsyc v ss rstc bsy rd nc reset int wr selc v ss nc sdc 6 cs as0 [a0] bhe [a1] dmard [a2] ale [a3] clk dfmode nc ad0 ad1 ad2 ad3 v ss v ss ad4 ad5 ad6 ad7 dreq v ss v ss v ss v ss v ss v ss v dd v dd sdc 0 sdc 1 sdc 2 sdc 3 sdc 4 sdc 5 sd 2 sd 3 v ss v ss sd 4 sd 5 sd 6 sd 7 sd p v ss v ss 31 32 33 34 35 36 37 38 39 40 41 42 43 45 46 47 48 49 50 44 AM53C96 100-pin pqfp 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 29 1 23 45678910111213141516171819202122232425262728 30 52 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 51 v ss v ss 16506c-9
p r e l i m i n a r y amd 7 am53c94/AM53C96 logic symbol sdc p busmd 1C0 * dfmode int cs wr rd am53c94/96 sd 7C0 sd p bsyc msg c/d i/o atn selc rstc reqc ackc sdc 7C0 bsy sel rst req ack * isel * tsel dma 15C0 dmap 1C0 dreq bhe [a1] as0 [a0] ale [a3] ad 7C0 dmard [a2] dack dmawr clk reset note: *pins available on the AM53C96 only. 16506c-10 related amd products part number description 85c30 enhanced serial communcaiton controller 26lsxx line drivers/receivers 33c93a enhanced cmos scsi bus interface controller 80c186 highly integrated 16-bit microprocessor 80c286 high-performance 16-bit 80286 microprocessor part number description am386 tm high-performance 32-bit microprocessor 80188 highly integrated 8-bit microprocessor 53c80a scsi bus controller 85c80 combination 53c80a scsi and 85c30 escc 53c94lv low voltage, high performance scsi controller
p r e l i m i n a r y amd 8 am53c94/AM53C96 ordering information standard products amd standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of: temperature range c = commercial package type j = 84-pin plcc (pl 084) k = 100-pin pqfp (pqr100) device number/description am53c94/AM53C96 high performance scsi conroller am53c94 AM53C96 AM53C96 k c valid combinations valid combinations list configurations planned to be supported in volume for this device. consult the lo- cal amd sales office to confirm availability of specific valid combinations or to check on newly released combinations. jc kc, kc/w valid combinations alternate packaging option /w = trimmed and formed in a tray (pqj100) blank = molded carrier ring (35 mm) /w
p r e l i m i n a r y amd 9 am53c94/AM53C96 scsi output connections am53c94 am53c94 single ended scsi bus configuration sdc 7C0 , p selc , bsyc , reqc , ackc , rstc sd 7C0 , p sel , bsy , req , ack , rst msg , c/d , i/o , atn 16506c-11
p r e l i m i n a r y amd 10 am53c94/AM53C96 scsi output connections AM53C96 AM53C96 single ended scsi bus configuration sdc 7C0 , p selc , bsyc , reqc , ackc , rstc sd 7C0 , p sel , bsy , req , ack , rst msg , c/d , i/o , atn dfmode v cc 16506c-12 sdc 7C0 , p selc , bsyc , rstc sd 7C0 , p sel , bsy , rst msg , c/d , i/o , req dfmode atn , ack AM53C96 differential scsi bus configuration tsel isel AM53C96 dt dt dt dt 16506c-13
p r e l i m i n a r y amd 11 am53c94/AM53C96 tsel vcc differential transceiver connections for the differential scsi bus configuration using 75als170 and 75als171 transceivers vcc selc gnd sel + sel C sel bsyc gnd bsy + bsy C bsy rstc gnd rst + rst C rst gnd 75als171 sdc 6 sd 6 C sd 6 + sd 6 sdc 7 sd 7 C sd 7 + sd 7 sdc p sd p C sd p + sd p 75als170 sdc 3 sd 3 C sd 3 + sd 3 sdc 4 sd 4 C sd 4 + sd 4 sdc 5 sd 5 C sd 5 + sd 5 75als170 sdc 0 sd 0 C sd 0 + sd 0 sdc 1 sd 1 C sd 1 + sd 1 sdc 2 sd 2 C sd 2 + sd 2 75als170 atn isel C atn + atn 75als170 C msg + msg C c/d tsel msg tsel c/d + c/d tsel i/o C i/o + i/o 75als170 reqc ackc req + req C req isel ack + ack C ack 75als171 gnd 16506c-14
p r e l i m i n a r y amd 12 am53c94/AM53C96 sdc 6 sd 6 differential transceiver connections for the differential scsi bus configuration using 75176a transceiver C sd 6 + sd 6 sd 6 sdc 6 rstc gnd rst + rst C rst gnd sdc 0 sd 0 C sd 0 + sd 0 sdc 0 sd 0 tsel msg C msg + msg msg tsel sdc 1 sd 1 C sd 1 + sd 1 sd 1 sdc 1 tsel c/d C c/d + c/d c/d tsel sdc 2 sd 2 C sd 2 + sd 2 sd 2 sdc 2 tsel i/o C i/o + i/o i/o tsel sdc 3 sd 3 C sd 3 + sd 3 sd 3 sdc 3 isel atn C atn + atn atn isel sdc 4 sd 4 C sd 4 + sd 4 sd 4 sdc 4 selc gnd sel + sel C sel gnd sdc 5 sd 5 C sd 5 + sd 5 sd 5 sdc 5 bsyc gnd bsy + bsy C bsy gnd sdc 7 sd 7 C sd 7 + sd 7 sd 7 sdc 7 tsel reqc req + req C req gnd sdc p sd p C sd p + sd p sd p sdc p isel ackc ack + ack C ack gnd 16506c-15
p r e l i m i n a r y amd 13 am53c94/AM53C96 pin description host interface signals dma 15C0 data/dma bus (input/output, active high, internal pull-up) the configuration of this bus depends on the bus mode 1C0 (busmd 1C0) inputs. when the device is config- ured for a single bus operation, the host can access the internal register set on the lower eight lines and the dma accesses can be made to the fifo using entire bus. when using the byte mode via the bhe and a0 inputs the data can be transferred on either the upper or lower half of the dma 15C0 bus. dmap 1C0 data/dma parity bus (input/output, active high, internal pull-up) these lines are odd parity for the dma 15C0 bus. dmap 1 is the parity for the upper half of the bus dma 15C8 and dmap 0 is the parity for the lower half of the bus dma 7C0. ale [a3] address latch enable [address 3] (input, active high) this is a dual function input. when the device is config- ured for the dual bus mode (two buses, multiplexed and byte control), this input acts as ale. as ale, this input latches the address on the ad 7C0 bus on its low going edge. when the device is configured for all other bus modes, this input acts as a3. as a3, this input is the third bit of the address bus. dmard [a2] dma read [address 2] (input, active low [active high]) this is a dual function input. when the device is config- ured for the dual bus mode (two buses, multiplexed and byte control), this input acts as dmard . as dmard , this input is the read signal for the dma 15C0 bus. when the device is configured for all other bus modes, this in- put acts as a2. as a2, this input is the second bit of the address bus. bhe [a1] bus high enable [address 1] (input, active high) this is a dual function input. when the device is config- ured for the dual bus mode (two buses, multiplexed and byte control), this input acts as bhe. as bhe, this input works in conjunction with as0 to indicate the lines on which data transfer will take place. when the device is configured for all other bus modes this input acts as a1. as a1, this input is the first bit of the address bus. as0 [a0] address status [address 0] (input, active high) this is a dual function input. when the device is config- ured for the dual bus mode (two buses, multiplexed and byte control), this input acts as as0. as as0, this input works in conjunction with bhe to indicate the lines on which data transfer will take place. when the device is configured for all other bus modes, this input acts as a0. as a0, this input is the zeroth bit of the address bus. the following is the decoding for the bhe and as0 inputs: bhe as0 bus used 1 1 upper bus C dma 15C8, dmap 1 1 0 full bus C dma 15C0, dmap 1C0 0 1 reserved 0 0 lower bus C dma 7C0, dmap 0 dreq dma request (output, active high, hi-z) this output signal to the dma controller will be active during dma read and write cycles. during a dma read cycle it will be active as long as there is a word (or a byte in the byte mode) in the fifo to be transferred to mem- ory. during a dma write cycle it will be active as long as there is an empty space for a word (or a byte in the byte mode) in the fifo. dack dma acknowledge (input, active low) this input signal from the dma controller will be active during dma read and write cycles. the dack signal is used to access the dma fifo only and should never be active simultaneously with the cs signal, which ac- cesses the registers only. ad 7C0 host address data bus (input/output, active high, internal pull-up) this bus is used only in the dual bus mode. this bus al- lows the host processor to access the devices internal registers while the dma bus is transferring data. when using multiplexed bus, these lines can be used for ad- dress and data. when using non multiplexed bus these lines can be used for the data only.
p r e l i m i n a r y amd 14 am53c94/AM53C96 dmawr dma write (input, active low) this signal writes the data on the dma 15C0 bus into the internal fifo when dack is also active. when in the single bus mode this signal must be tied to the wr signal. rd read (input active low) this signal reads the internal device registers and places their contents on the data bus, when either cs signal or dack signal is active. wr write (input active low) this signal writes the internal device registers with the value present on the data bus, when the cs signal is also active. cs chip select (input active low) this signal enables the read and write of the device reg- isters. cs enables access to any register (including the fifo) while the dack enables access only to the fifo. cs and dack should never be active simultaneously in the single bus mode, they may however be active simul- taneously in the dual bus mode provided the cs signal is not enabling access to the fifo. int interrupt (output, active low, open drain) this signal is a non maskable interrupt flag to the host processor. this signal is latched on the output on the high going edge of the clock. this flag may be cleared by reading the interrupt status register (istat) or by per- forming a device reset (hard or soft). this flag is not cleared by a scsi reset. dfmode differential mode (input, active low) this input is available only on the AM53C96. this input configures the scsi bus to either single ended or differ- ential mode. when this input is active, the device oper- ates in the differential scsi mode. the scsi data is available on the sd 7C0 lines and the high active trans- ceiver enables on the sdc 7C0 outputs. when this input is inactive, the device operates in the single ended scsi mode. the scsi input data is available on sd 7C0 lines and the output data is available on sdc 7C0 lines. in the single ended scsi mode, the sd 7C0 and the sdc 7C0 buses can be tied together externally. busmd 1C0 bus mode (input, active high) these inputs configure the device for single bus or dual bus operation and the dma width. busmd1 busmd0 bus configuration 1 1 two buses: 8-bit host bus and 16-bit dma bus register address on a 3C0 and data on ad bus 1 0 two buses: multiplexed and byte control register address on ad 3C0 and data on ad bus 0 1 single bus: 8-bit host bus and 16-bit dma bus register address on a 3C0 and data on dma bus 0 0 single bus: 8-bit host bus and 8-bit dma bus register address on a 3C0 and data on dma bus clk clock (input) clock input used to generate all the internal device tim- ings. the maximum frequency of this input is 25 mhz. and a minimum of 10 mhz to maintain the scsi bus timings. reset reset (input, active high) this input when active resets the device. the reset in- put must be active for at least two clk periods after the voltage on the power inputs have reached vcc minimum. scsi interface signals sd 7C0 scsi data (input/output, active low, schmitt trigger) when the device is configured in the single ended scsi mode ( dfmode inactive) these pins are defined as in- puts for the scsi data bus. when the device is config- ured in the differential scsi mode ( dfmode active) these pins are defined as bidirectional scsi data bus.
p r e l i m i n a r y amd 15 am53c94/AM53C96 sd p scsi data parity (input/output, active low, schmitt trigger) when the device is configured in the single ended scsi mode ( dfmode inactive) this pin is defined as the input for the scsi data parity. when the device is configured in the differential scsi mode ( dfmode active) this pin is defined as bidirectional scsi data parity. sdc 7C0 scsi data control (output, active low, open drain) when the device is configured in the single ended scsi mode ( dfmode inactive) these pins are defined as out- puts for the scsi data bus. when the device is config- ured in the differential scsi mode ( dfmode active) these pins are defined as direction controls for the exter- nal differential transceivers. in this mode, a signal high state corresponds to an output to the scsi bus and a low state corresponds to an input from the scsi bus. sdc p scsi data control parity (output, active low, open drain) when the device is configured in the single ended scsi mode ( dfmode inactive) this pin is defined as an out- put for the scsi data parity. when the device is config- ured in the differential scsi mode ( dfmode active) this pin is defined as the direction control for the external differential transceiver. in this mode, a signal high state corresponds to an output to the scsi bus and a low state corresponds to an input from the scsi bus. msg message (input/output, active low, schmitt trigger) this is a bidirectional signal with 48 ma output driver. it is an output in the target mode and a schmitt trigger in- put in the initiator mode. c/d command/data (input/output, schmitt trigger) this is a bidirectional signal with 48 ma output driver. it is an output in the target mode and a schmitt trigger in- put in the initiator mode. i/o input/output (input/output, schmitt trigger) this is a bidirectional signal with 48 ma output driver. it is an output in the target mode and a schmitt trigger in- put in the initiator mode. atn attention (input/output, active low, schmitt trigger) this signal is a 48 ma output in the initiator mode and a schmitt trigger input in the target mode. this signal will be asserted when the initiator detects a parity error or it can be asserted via certain initiator commands. bsy busy (input, active low, schmitt trigger) this is a scsi input signal with a schmitt trigger. sel select (input, active low, schmitt trigger) this is a scsi input signal with a schmitt trigger. rst reset (input, active low, schmitt trigger) this is a scsi input signal with a schmitt trigger. req request (input, active low, schmitt trigger) this is a scsi input signal with a schmitt trigger. ack acknowledge (input, active low, schmitt trigger) this is a scsi input signal with a schmitt trigger. bsyc busy control (output, active low, open drain) this is a scsi output with 48 ma drive. when the device is configured in the single ended scsi mode ( dfmode inactive) this pin is defined as a bsy output for the scsi bus. when the device is configured in the differential scsi mode ( dfmode active) this pin is defined as the direction control for the external differential transceiver. in this mode, a signal high state corresponds to an out- put to the scsi bus and a low state corresponds to an input from the scsi bus.
p r e l i m i n a r y amd 16 am53c94/AM53C96 selc select control (output, active low, open drain) this is a scsi output with 48 ma drive. when the device is configured in the single ended scsi mode ( dfmode inactive) this pin is defined as a sel output for the scsi bus. when the device is configured in the differential scsi mode ( dfmode active) this pin is defined as the direction control for the external differential transceiver. in this mode, a signal high state corresponds to an out- put to the scsi bus and a low state corresponds to an input from the scsi bus. rstc reset control (output, active low, open drain) this is a scsi output with 48 ma drive. the reset scsi command will cause the device to drive rstc active for 25 msC40 ms, which will depend on the clk frequency and the conversion factor. when the device is config- ured in the single ended scsi mode ( dfmode inac- tive) this pin is defined as a rst output for the scsi bus. when the device is configured in the differential scsi mode ( dfmode active) this pin is defined as the direc- tion control for the external differential transceiver. in this mode, a signal high state corresponds to an output to the scsi bus and a low state corresponds to an input from the scsi bus. reqc request control (output, active low, open drain) this is a scsi output with 48 ma drive. this signal is ac- tivated only in the target mode. ackc acknowledge control (output, active low, open drain) this is a scsi output with 48 ma drive. this signal is ac- tivated only in the initiator mode. isel initiator select (output, active high) this signal is available on the AM53C96 only. this sig- nal is active whenever the device is in the initiator mode. in the differential mode this signal is used to enable the initiator signals ackc and atn and the device also drives these signals. tsel target select (output, active high) this signal is available on the AM53C96 only. this sig- nal is active whenever the device is in the target mode. in the differential mode this signal is used to enable the target signals reqc , msg , c/d and i/o and the device also drives these signals. functional description register map address (hex.) operation register 00 read current transfer count register lsb 00 write start transfer count register lsb 01 read current transfer count register msb 01 write start transfer count register msb 02 read/write fifo register 03 read/write command register 04 read status register 04 write scsi destination id register 05 read interrupt status register 05 write scsi timeout register address (hex.) operation register 06 read internal state register 06 write synchronous transfer period register 07 read current fifo/internal state register 07 write synchronous offset register 08 read/write control register 1 09 write clock factor register 0a write forced test mode register 0b read/write control register 2 0c read/write control register 3 0f write data alignment register note: not all registers in this device are both readable and writable. some read only registers share the same address with write only registers. the registers can be accessed by asserting the cs signal and then asserting either rd or wr signal depending on the operation to be performed. only the fifo register can be accessed by asserting either cs or dack in conjunction with rd and wr signals or dmard and dmawr signals. the register address inputs are ignored when dack is used but must be valid when cs is used.
p r e l i m i n a r y amd 17 am53c94/AM53C96 current transfer count register (00hC01h) read only current transfer count register ctcreg address: 00 hC 01 h type: read 15 14 13 12 11 10 9 8 crvl15 crvl14 crvl13 crvl12 crvl11 crvl10 crvl9 crvl8 xxxxxxxx 76543210 crvl7 crvl6 crvl5 crvl4 crvl3 crvl2 crvl1 crvl0 xxxxxxxx 16506c-16 ctcreg C bits 15:0 C crvl 15:0 C current value 15:0 this is a two-byte register. it counts down to keep track of the number of dma transfers. reading this registers will return the current value of the counter. the counter will decrement by one for every byte transferred and two for every word transferred over the scsi bus. the trans- action is complete when the count reaches zero. these registers are automatically loaded with the values in the start transfer count register every time a dma com- mand is issued. in the target mode, this counter is decremented by the active edge of dack during the data-in phase and by reqc during the data-out phase. in the initiator mode, the counter is decremented by the active edge of dack during the synchronous data-in phase or by ackc during the asynchronous data-in phase and by dack during the data-out phase. start transfer count register (00hC01h) write only start transfer count register stcreg address: 00 hC 01 h type: write 15 14 13 12 11 10 9 8 stvl15 stvl14 stvl13 stvl12 stvl11 stvl10 stvl9 stvl8 xxxxxxxx 76543210 stvl7 stvl6 stvl5 stvl4 stvl3 stvl2 stvl1 stvl0 xxxxxxxx 16506c-017 stcreg C bits 15:0 C stvl 15:0 C start value 15:0 this is a two-byte register. it contains the number of bytes to be transferred during a dma operation. the value of this register is set to the number of bytes to be transferred prior to a dma transfer command. this reg- ister retains its programmed value until it is overwritten and is not affected by hardware or software reset. therefore, it is not necessary to reprogram the count for subsequent dma transfers of the same size. writing a zero to this register sets a maximum transfer count of 65536 bytes. the value in this register is undefined at power-up. fifo register (02h) read/write fifo register ffreg address: 02 h type: read/write 76543210 ff7 ff6 ff5 ff4 ff3 ff2 ff1 ff0 00000000 16506c-18 ffreg C bits 7:0 C ff 7:0 C fifo 7:0 the bottom of the 16x9 fifo is mapped into the fifo register address. by reading and writing this register the bottom of the fifo can be read or written. this is the only register that can also be accessed by dack along with dmard or dmawr . this register is reset to zero by hardware or software reset and also at the start of a selection or reselection sequence. command register (03h) read/write command register cmdreg address: 03 h type: read/write 76543210 dma cmd6 cmd5 cmd4 cmd3 cmd2 cmd1 cmd0 xxxxxxxx command 6:0 direct memory access 16506c-019 commands to the device are issued by writing to this register. this register is two deep which allows for com- mand queuing. the second command can be issued be- fore the first one is completed. the reset command and the stop dma command are not queued and are exe- cuted immediately. reading this register will return the command currently being executed (or the last com- mand executed if there are no pending commands).
p r e l i m i n a r y amd 18 am53c94/AM53C96 cmdreg C bit 7 C dma C direct memory access the dma bit when set notifies the device that the com- mand is a dma instruction, when reset it is a non-dma instruction. for dma instructions the current transfer count register (ctcreg) will be loaded with the con- tents of the start transfer count register (stcreg). the data is then transferred and the ctcreg is decre- mented for each byte until it reaches zero. cmdreg C bits 6:0 C cmd 6:0 C command 6:0 these command bits decode the commands that the device needs to perform. there are a total of 29 commands grouped into four categories. the groups are initiator commands, target commands, selection/ reselection commands and general purpose com- mands. initiator commands cmd6 cmd5 cmd4 cmd3 cmd2 cmd1 cmd0 command 0010000 information transfer 00100 01 initiator command complete steps 0010010 message accepted 0011000 transfer pad bytes 0011010 set atn 0011011 reset atn target commands cmd6 cmd5 cmd4 cmd3 cmd2 cmd1 cmd0 command 0100000 send message 0100001 send status 0100010 send data 0100011 disconnect steps 0100100 terminate steps 0100101 target command complete steps 0100111 disconnect 0101000 receive message steps 0101001 receive command 0101010 receive data 0101011 receive command steps 0000100dma stop idle commands cmd6 cmd5 cmd4 cmd3 cmd2 cmd1 cmd0 command 1000000 reselect steps 10000 01 select without atn steps 1000010 select with atn steps 1000011 select with atn and stop steps 1000100 enable selection/reselection 1000101 disable selection/reselection 1000110 select with atn3 steps general commands cmd6 cmd5 cmd4 cmd3 cmd2 cmd1 cmd0 command 0000000no operation 00000 01 clear fifo 0000010 reset device 0000011 reset scsi bus
p r e l i m i n a r y amd 19 am53c94/AM53C96 status register (04h) read status register statreg address: 04 h type: read 76543210 int ioe pe ctz gcv msg c/d i/o 0000 0 xxx illegal operation error parity error count to zero group code valid message command/data input/output interrupt 16506c-20 this read only register contains flags to indicate the status and phase of the scsi transactions. it indicates whether an interrupt or error condition exists. it should be read every time the host is interrupted to determine which device is asserting an interrupt. the data is latched until the interrupt status register is read. the phase bits will be latched only if latching is enabled in the control register 2, otherwise, it will indicate the current scsi phase. if command stacking is used, two inter- rupts might occur. reading this register will clear the status information for the first interrupt and update the status register for the second interrupt. statreg C bit 7 C int C interrupt the int bit is set when the device asserts the interrupt output. this bit will be cleared by a hardware or software reset. reading the interrupt status register will deas- sert the interrupt output and also clear this bit. statreg C bit 6 C ioe C illegal operation error the ioe bit is set when an illegal operation is attempted. this condition will not cause an interrupt, it will be de- tected by reading the status register while servicing an- other interrupt. the following conditions will cause the ioe bit to be set: n dma and scsi transfer directions are opposite. n fifo overflows. n in initiator mode an unexpected phase change detected during synchronous data transfer. n command register overwritten. this bit will be cleared by reading the interrupt status register or by a hard or soft reset. statreg C bit 5 C pe C parity error the pe bit is set if the parity checking option is enabled in control register 1 and the device detects a parity er- ror on incoming scsi data, command, status or mes- sage bytes. detection of a parity error condition will not cause an interrupt but will be reported with other inter- rupt causing conditions. when a parity error is detected in the information phase of the initiator mode atn is as- serted on the scsi bus. this bit will be cleared by reading the interrupt status register or by a hard or soft reset. statreg C bit 4 C ctz C count to zero the ctz bit is set when the current transfer count register (ctcreg) has counted down to zero. this bit will be reset when the ctcreg is written. reading the interrupt status register will not affect this bit. this bit will however be cleared by a hard or soft re- set. note: a non-dma nop will not reset the ctz bit since it does not load the ctcreg but a dma nop will reset this bit since it loads the ctcreg. statreg C bit 3 C gcv C group code valid the gcv bit is set if the group code field in the com- mand descriptor block (cdb) is one that is defined by the ansi committee in their document x3.131 C 1986. if the scsi-2 feature enable (s2fe) bit in the control register 2 (cntlreg2) is set, group 2 commands will be treated as ten byte commands and the gcv bit will be set. if s2fe is reset then group 2 commands will be treated as reserved commands. group 3 and 4 com- mand will always be considered as reserved com- mands. the device will treat all reserved commands as six byte commands. group 6 commands will always be treated as vendor unique six byte commands and group 7 commands will always be treated as vendor unique ten byte commands. the gcv bit is cleared by reading the interrupt status register (instreg) or by a hard or soft reset.
p r e l i m i n a r y amd 20 am53c94/AM53C96 statreg C bit 2 C msg C message statreg C bit 1 C c/d C command/data statreg C bit 0 C i/o C input/output bit2 bit1 bit0 msg c/d i/o scsi phase 1 1 1 message in 1 1 0 message out 1 0 1 reserved 1 0 0 reserved 0 1 1 status 0 1 0 command 0 0 1 data_in 0 0 0 data_out the msg, c/d and i/o bits together can be referred to as the scsi phase bits. they indicate the phase of the scsi bus. these bits may be latched or unlatched de- pending on the option selected in control register 2 (cntlreg2) by the latch scsi phase (lsp) bit. in the latched mode the scsi phase bits are latched at the end of a command and the latch is opened when the interrupt status register (instreg) is read. in the un- latched mode, they indicate the phase of the scsi bus when this register is read. scsi destination id register (04h) write res res res res res 00000 scsi destination id register sdidreg address: 04 h type: write 76543210 did2 did1 did0 xxx reserved reserved reserved reserved scsi destination id 2:0 reserved 16506c-21 sdidreg C bits 7:3 C res C reserved sdidreg C bits 2:0 C did 2:0 C destination id 2:0 the did 2:0 bits are the encoded scsi id of the device on the scsi bus which needs to be selected or reselected. did2 did1 did0 scsi id 1117 1106 1015 1004 0113 0102 0011 0000 at power-up the state of these bits is undefined. the did 2:0 bits are not affected by reset.
p r e l i m i n a r y amd 21 am53c94/AM53C96 interrupt status register (05h) read srst icmd dis sr so 00000 interrupt status register instreg address: 05h type: read 76543210 resel sela sel 000 invalid command disconnected service request successful operation selected with attention scsi reset 16506c-22 selected reselected the interrupt status register (instreg) will indicate the reason for the interrupt. this register is used with the status register (statreg) and internal status regis- ter (isreg) to determine the reason for the interrupt. reading the instreg will clear all three registers. instreg C bit 7 C srst C scsi reset the srst bit will be set if a scsi reset is detected and scsi reset reporting is enabled via the disr (bit 6) of the cntlreg1. instreg C bit 6 C icmd C invalid command the icmd bit will be set if the device detects an illegal command code. this bit is also set if a command code from a different mode is detected than the mode the de- vice is currently in. instreg C bit 5 C dis C disconnected the dis bit can be set in the target or the initiator mode when the device disconnects from the scsi bus. in the target mode this bit will be set if a terminate or a com- mand complete sequence causes the device to discon- nect from the scsi bus. in the initiator mode this bit will be set if the target disconnects or a selection or reselec- tion timeout occurs. instreg C bit 4 C sr C service request the sr bit can be set in the target or the initiator mode when another device on the scsi bus has a service re- quest. in the target mode this bit will be set when the in- itiator asserts the atn signal. in the initiator mode this bit is set whenever the target requests an information transfer phase. instreg C bit 3 C so C successful operation the so bit can be set in the target or the initiator mode when an operation is successfully complete. in the target mode this bit will be set when any target mode command is completed. in the initiator mode this bit is set after a target has been successfully selected, after a command is successfully completed and after an infor- mation transfer command when the target requests a message in phase. instreg C bit 2 C resel C reselected the resel bit is set at the end of the reselection phase indicating that the device has been reselected as an in- itiator. instreg C bit 1 C sela C selected with attention the sela bit is set at the end of the selection phase indi- cating that the device has been selected and that the atn signal was active during the selection. instreg C bit 0 C sel C selected the sel bit is set at the end of the selection phase indi- cating that the device has been selected and that the atn signal was inactive during the selection.
p r e l i m i n a r y amd 22 am53c94/AM53C96 scsi timeout register (05h) write scsi timeout register stimreg address: 05 h type: write 76543210 stim7 stim6 stim5 stim4 stim3 stim2 stim1 stim0 xxxxxxxx 16506c-23 this register determines how long the initiator (target) will wait for a target to respond to a selection (reselec- tion) before timing out. it should be set to yield 250 ms to comply with ansi standards for scsi. stimreg C bits 7:0 C stim 7:0 C scsi timer 7:0 the value loaded in stim 7:0 can be calculated from the following formula: stim 7:0 = [(scsi time out) (clock frequency) / (8192 (clock factor))] example: scsi time out (in seconds): 250 ms. (recommended by the ansi standard) = 250 x 10 C3 s. clock frequency: 20 mhz. (assume) = 20 x 10 6 hz. clock factor: clkf 2:0 from clock conversion regis- ter (09h) = 5 stim 7:0 = (250 x 10 C3 ) x (20 x 10 6 ) / (8192 (5)) = 122 decimal internal state register (06h) read internal state register isreg address: 06 h type: read 76543210 res res res res sof is2 is1 is0 xxxx 0 000 reserved reserved reserved synchronous offset flag internal state 2:0 reserved 16506c-24 the internal state register (isreg) tracks the progress of a sequence-type command. it is updated after each successful completion of an intermediate operation. if an error occurs, the host can read this register to deter- mined at where the command failed and take the neces- sary procedure for recovery. reading the interrupt status register will clear this register. isreg C bits 7:4 C res C reserved isreg C bit 3 C sof C synchronous offset flag the sof is reset when the synchronous offset register (sofreg) has reached its maximum value. note: the sof bit is active low. isreg C bits 2:0 C is 2:0 C internal state 2:0 the is 2:0 bits along with the interrupt status register (instreg) indicates the status of the successfully completed intermediate operation. refer to the status decode section for more details.
p r e l i m i n a r y amd 23 am53c94/AM53C96 initiator select without atn steps internal state interrupt status register (06h) register (05h) explanation bits 2:0 (hex) bits 7:0 (hex) 0 20 arbitration steps completed or disconnected or selection timeCout 4 18 selection with atn steps fully executed 3 18 sequence halted during command transfer due to premature phase change (target) 2 18 arbitration and selection completed; sequence halted because target failed to assert command phase initiator select with atn steps internal state interrupt status register (06h) register (05h) explanation bits 2:0 (hex) bits 7:0 (hex) 4 18 selection with atn steps fully executed 3 18 sequence halted during command transfer due to premature phase change; some cdb bytes may not have been sent; check fifo flags 2 18 message out completed; sent one message byte with atn true, then released atn; sequence halted because target failed to assert command phase after message byte was sent 0 18 arbitration and selection completed; sequence halted because target did not assert message out phase; atn still driven by hpsc initiator select with atn3 steps internal state interrupt status register (06h) register (05h) explanation bits 2:0 (hex) bits 7:0 (hex) 0 20 arbitration steps completed or disconnected or selection timeCout 4 18 selection with atn3 steps fully executed 3 18 sequence halted during command transfer due to premature phase change; some cdb bytes may not have been sent; check fifo flags 2 18 one, two, or three message bytes sent; sequence halted because target failed to assert command phase after third message byte, or prematurely released message out phase; atn released only if third message byte was sent 0 18 arbitration and selection completed; sequence halted because target failed to assert message out phase; atn still driven by hpsc initiator select with atn and stop steps internal state interrupt status register (06h) register (05h) explanation bits 2:0 (hex) bits 7:0 (hex) 0 20 arbitration steps completed or disconnected or selection timeCout 0 18 arbitration and selection completed; sequence halted because target failed to assert message out phase; atn still asserted by hpsc 1 18 message out completed; one message byte sent; atn on
p r e l i m i n a r y amd 24 am53c94/AM53C96 target selected without atn steps internal state interrupt status register (06h) register (05h) explanation bits 2:0 (hex) bits 7:0 (hex) 2 11 selected; received entire cdb; check group code valid bit; initiator asserted atn in command phase 1 11 sequence halted in command phase due to parity error; some cdb bytes may not have been received; check fifo flags; initiator asserted atn in command phase 2 01 selected; received entire cdb; check group code valid bit 1 01 sequence halted in command phase because of parity error; some cdb bytes may not have been received; check fifo flags 0 01 selected; loaded bus id into fifo; nullCbyte message loaded into fifo target select with atn steps, scsiC2 bit not set internal state interrupt status register (06h) register (05h) explanation bits 2:0 (hex) bits 7:0 (hex) 2 12 selection complete; received one message byte and entire cdb; initiator as- serted atn during command phase 1 12 halted in command phase; parity error and atn true 0 12 selected with atn; stored bus id and one message byte; sequence halted be- cause atn remained true after first message byte 2 02 selection completed; received one message byte and the entire cdb 1 02 sequence halted in command phase because of parity error; some cdb bytes not received; check group code valid bit and fifo flags 0 02 selected with atn; stored bus id and one message byte; sequence halted be- cause of parity error or invalid id message target select with atn steps, scsiC2 bit set internal state interrupt status register (06h) register (05h) explanation bits 2:0 (hex) bits 7:0 (hex) 5 12 halted in command phase; parity error and atn true 4 12 atn remained true after third message byte 0 02 selected with atn; stored bus id and one message byte; sequence halted be- cause of parity error or invalid id message 6 02 selection completed; received three message bytes and the entire cdb 5 02 received three message bytes then halted in command phase because of parity error; some cdb bytes not received; check group code valid bit and fifo flags 402parity error during second or third message byte target receive command steps internal state interrupt status register (06h) register (05h) explanation bits 2:0 (hex) bits 7:0 (hex) 2 18 received entire cdb; initiator asserted atn 1 18 sequence halted during command transfer due to parity error; atn asserted by initiator 2 08 received entire cdb 1 08 sequence halted during command transfer due to parity error; check fifo flags target disconnect steps internal state interrupt status register (06h) register (05h) explanation bits 2:0 (hex) bits 7:0 (hex) 2 28 disconnect steps fully executed; disconnected; bus is free 1 18 two message bytes sent; sequence halted because initiator asserted atn 0 18 one message byte sent; sequence halted because initiator asserted atn
p r e l i m i n a r y amd 25 am53c94/AM53C96 target terminate steps internal state interrupt status register (06h) register (05h) explanation bits 2:0 (hex) bits 7:0 (hex) 2 28 terminate steps fully executed; disconnected; bus is free 1 18 status and message bytes sent; sequence halted because initiator asserted atn 0 18 status byte sent; sequence halted because initiator asserted atn target command complete steps internal state interrupt status register (06h) register (05h) explanation bits 2:0 (hex) bits 7:0 (hex) 1 18 status and message bytes sent; sequence halted because initiator set atn 0 18 status byte sent; sequence halted because initiator set atn 2 08 command complete steps fully executed
p r e l i m i n a r y amd 26 am53c94/AM53C96 synchronous transfer period register (06h) write 6 synchronous transfer period register stpreg address: 06 h type: write 7 543210 res res res stp4 stp3 stp2 stp1 stp0 xxx0 0 101 reserved reserved synchronous transfer period 4:0 reserved 16506c-25 the synchronous transfer period register (stpreg) contains a 5-bit value indicating the number of clock cy- cles each byte will take to be transferred over the scsi bus in synchronous mode. the minimum value allowed is 5. the stpreg defaults to five after a hard or soft reset. stpreg C bits 7:5 C res C reserved stpreg C bits 4:0 C stp 4:0 C synchronous transfer period 4:0 the stp 4:0 bits are programmed to specify the syn- chronous transfer period or the number of clock cycles for each byte transfer in the synchronous mode. the minimum value for stp 4:0 is five. missing table entries follow the binary code. clocks/ stp4 stp3 stp2 stp1 stp0 byte 0 01005 0010 15 0 01106 0 01117 1 111131 0 000032 0 000133 0 001034 0 001135
p r e l i m i n a r y amd 27 am53c94/AM53C96 current fifo/internal state register (07h) read current fifo/internal state register cfisreg address: 07 h type: read 76543210 is2 is1 is0 cf4 cf3 cf2 cf1 cf0 0000 0 000 internal state 2:0 current fifo 4:0 16506c-26 this register has two fields, the current fifo field and the internal state field. cfisreg C bits 7:5 C is 2:0 C internal state 2:0 the internal state register (isreg) tracks the progress of a sequence-type command. the is 2:0 bits are duplicated from the is 2:0 field in the internal state register (isreg) in the normal mode. if the device is in the test mode, is 0 is set to indicate that the offset value is non zero. a non zero value indicates that synchronous data transfer can continue. a zero value indicates that the synchronous offset count has been reached and no more data can be transferred until an acknowledge is received. cfisreg C bits 4:0 C cf 4:0 C current fifo 4:0 the cf 4:0 bits are the binary coded value of the num- ber of bytes in the fifo. these bits should not be read when the device is transferring data since this count may not be stable. synchronous offset register (07h) write synchronous offset register sofreg address: 07 h type: write 76543210 so3 so2 so1 so0 res res res res xxxx 0 000 reserved reserved reserved synchronous offset 3:0 reserved 16506c-27 the synchronous offset register (sofreg) contains a 4-bit count of the number of bytes that can be sent to (or received from) the scsi bus without an ack (or req ). bytes exceeding the threshold will be sent one byte at a time (asynchronously). that is, each byte will require an ack / req handshake. to set up an asyn- chronous transfer, the sofreg is set to zero. the sofreg is set to zero after a hard or soft reset. sofreg C bits 7:4 C res C reserved sofreg C bits 3:0 C so 3:0 C synchronous offset 3:0 the so 4:0 bits are the binary coded value of the num- ber of bytes that can be sent to (or received from) the scsi bus without an ack (or req ) signal.
p r e l i m i n a r y amd 28 am53c94/AM53C96 control register one (08h) read/write control register one cntlreg1 address: 08 h type: read/write 76543210 etm disr pte pere ste cid2 cid1 cid0 0000 0 xxx disable interrupt on scsi reset parity test enable parity error reporting enable self test enable chip id 2:0 extended timing mode 16506c-28 the control register 1 (cntlreg1) sets up the device with various operating parameters. cntlreg1 C bit 7 C etm C extended timing mode the etm bit is set if an extra clock period is required be- tween the data being driven on the bus and the req or ack being asserted. this is some times necessary in high capacitive loading environments. the etm bit is re- set to zero by a hard or soft reset. cntlreg1 C bit 6 C disr C disable interrupt on scsi reset the disr bit masks the reporting of the scsi reset. when the disr bit is set and a scsi reset is asserted, the device will disconnect from the scsi bus and remain idle without interrupting the host processor. when the disr bit is reset and a scsi reset is asserted the device will respond by interrupting the host processor. the disr bit is reset to zero by a hard or soft reset. cntlreg1 C bit 5 C pte C parity test enable the pte bit is for test use only. when the pte bit is set the parity on the output (scsi or host processor) bus is forced to the value of the msb (bit 7) of the output data from the internal fifo. this allows parity errors to be created to test the hardware and software. the pte bit is reset to zero by a hard or soft reset. cntlreg1 C bit 4 C pere C parity error report- ing enable the pere bit enables the checking and reporting of par- ity errors on incoming scsi bytes during the information transfer phase. when the pere bit set and a bad parity is detected, the pe bit in the statreg is will be set but an interrupt will not be generated. in the initiator mode the atn signal will also be asserted on the scsi bus. when the pere bit is reset and a bad parity occurs it is not detected and no action is taken. cntlreg1 C bit 3 C ste C self test enable the ste bit is for test use only. when the ste bit is set the device is placed in a test mode which enables the device to access the test register at address 0ah. to re- set this bit and to resume normal operation the device must be issued a hard or soft reset. cntlreg1 C bit 2:0 C cid 2:0 C chip id 2:0 the chip id 2:0 bits specify the binary coded value of the device id on the scsi bus. the device will arbitrate with this id and will respond to selection or reselection to this id. at power-up the state of these bit are undefined. these bits are not affected by hard or soft reset.
p r e l i m i n a r y amd 29 am53c94/AM53C96 clock factor register (09h) write 3 clock factor register clkfreg address: 09 h type: write 7654 210 res res res res res clkf2 clkf1 clkf0 xxxxx010 reserved reserved reserved reserved clock factor 2:0 reserved 16506c-29 the clock factor register (clkfreg) must be set to indicate the input frequency range of the device. this value is crucial for controlling various timings to meet the scsi specification. the selector can be calculated by rounding off the quotient of (input clock frequency in mhz)/(5 mhz). the device has a frequency range of 10 to 25 mhz. clkfreg C bits 7:3 C res C reserved clkfreg C bits 2:0 C clkf 2:0 C clock factor 2:0 the clkf 2:0 bits specify the binary coded value of the clock factor. the clkf 2:0 bits will default to a value of 2 by a hard or soft reset. input clock clkf2 clkf1 clkf0 frequency in mhz 01 0 10 0 1 1 10.01 to 15 1 0 0 15.01 to 20 1 0 1 20.01 to 25 forced test mode register (0ah) write 3 forced test mode register ftmreg address: 0a h type: write 7654 210 res res res res res fhi fim ftm xxxxx000 reserved reserved reserved reserved forced high impedance mode forced initiator mode forced target mode reserved 16506c-30 the forced test mode register (ftmreg) is for test use only. the ste bit in the cntlreg1 must be set for the ftmreg to operate. ftmreg C bits 7:3 C res C reserved ftmreg C bit 2 C fhi C forced high impedance mode the fhi bit when set places all the output and bidirec- tional pins into a high impedance state.
p r e l i m i n a r y amd 30 am53c94/AM53C96 ftmreg C bit 1 C fim C forced initiator mode the fim bit when set forces the device into the initiator mode. the device will then execute all initiator com- mands irrespective of the scsi bus status. ftmreg C bit 0 C ftm C forced target mode the ftm bit when set forces the device into the target mode. the device will then execute all target commands irrespective of the scsi bus status. control register two (0bh) read/write control register two cntlreg2 address: 0b h type: read/write 76543210 dae lsp sbo tsdr s2fe acdpe pgrp pgdp 0000 0 000 latch scsi phase select byte order triCstate dma request scsiC2 features enable abort on command/data parity error pass through/generate register parity pass through/generate data parity data alignment enable 16506c-31 the control register 2 (cntlreg2) sets up the device with various operating parameters. cntlreg2 C bit 7 C dae C data alignment enable the dae bit is used in the initiator synchronous data-in phase only. when the dae bit is set one byte is reserved at the end of the fifo when the phase changes to the synchronous data-in phase. the contents of this byte will become the lower byte of the dma word (16-bit) transfer to the memory, the upper byte being the first byte of the first word received from the scsi bus. note: if an interrupt is received for a misaligned boundary on a phase change to synchronous data the following recov- ery procedure may be followed. the host processor should copy the byte at the start address in the host memory to the data alignment register 0fh (dalreg) and then issue an information transfer command. the first word the device will write to the memory (via dma) will consists of the lower byte from the dalreg and the upper byte from the first byte received from the scsi bus. the dae bit must be set before the phase changes to the synchronous data-in. the dae bit is reset to zero by a hard or soft reset or by writing the dalreg when in- terrupted in the synchronous data-in phase. cntlreg2 C bit 6 C lsp C latch scsi phase the lsp bit is used to enable or disable the latching of the scsi phase bits (msg, c/d and i/o) in the status register (statreg) 04h. when the lsp bit is set the phase bits ststreg C bits 2:0 are latched at the end of each command. this simpli- fies software for stacked commands. when the lsp bit is reset the phase bits statreg C bits 2:0 reflect the actual state of the scsi phase lines at any instant of time. the lsp bit is reset by a hard or soft reset. cntlreg2 C bit 5 C sbo C select byte order the sbo bit is used only when the busmd 1:0 = 10 to enable or disable the byte control on the dma interface. when sbo is set and the busmd 1:0 = 10, the byte con- trol inputs bhe and as0 control the byte positions. when sbo is reset the byte control inputs bhe and as0 are ignored. cntlreg2 C bit 4 C tsdr C tri-state dma request the tsdr bit when set sends the dreq output signal to high impedance state and the device ignores all activity on the dma request (dreq) input. this is useful for wiring-or several devices that share a common dma request line. when the tsdr bit is reset the dreq output is driven to ttl levels. cntlreg2 C bit 3 C s2fe C scsiC2 features enable the s2fe bit allows the device to recognize two scsi-2 features. the two features are extended message fea- ture and the group 2 command recognition. extended message feature: when the s2fe bit is set and the device is selected with attention, the device will monitor the atn signal at the end of the first message byte. if the atn signal is active, the device will request two more message bytes before switching to the com- mand phase. if the atn signal is inactive the device will switch to the command phase. when the s2fe bit is re- set the device as a target will request a single message byte. as an initiator, the device will abort the selection sequence if the target does not switch to the command phase after receiving a single message byte.
p r e l i m i n a r y amd 31 am53c94/AM53C96 group 2 command recognition: when the s2fe bit is set the group 2 commands are recognized as 10 byte commands. the gcv (group code valid) bit in the statreg (04h) is set. when the s2fe bit is reset, the device will interpret the group 2 commands as reserved commands and will request 6 byte commands. the gcv bit in the statreg will not be set in this case. cntlreg2 C bit 2 C acdpe C abort on command/ data parity error the acdpe bit when set allows the device to abort a command or data transfer when a parity error is de- tected. when the acdpe bit is reset parity error is ig- nored. cntlreg2 C bit 1 C pgrp C pass through/gener- ate register parity the pgrp bit when set causes the data along with the parity from the host to pass through to the fifo under the control of the cs and the wr signals. when the pgrp bit is reset, the device generates the parity on the data from the host before writing it to the fifo. when the device is placing the data on the scsi bus, it will check for an outgoing parity error if either the pgrp bit is set or the pgdp (pass through/generate data parity) bit is set. cntlreg2 C bit 0 C pgdp C pass through/gener- ate data parity the pgdp bit when set causes the data along with the parity from the host to pass through to the fifo under the control of the dack and the wr signals. when the pgdp bit is reset, the device generates the parity on the data from the host before writing it to the fifo. when the device is placing the data on the scsi bus, it will check for an outgoing parity error if either the pgdp bit is set or the pgrp (pass through/generate register parity) bit is set. 4 control register three cntlreg3 address: 0c h type: read/write 765 3210 res res res res res lbtm mdm bs8 00000000 reserved reserved reserved reserved last byte transfer mode modify dma mode burst size 8 reserved 16506c-32 control register three (0ch) read/write cntlreg3 C bits 7:3 C res C reserved cntlreg3 C bit 2 C lbtm C last byte transfer mode the lbtm bit specifies how the last byte in an odd byte transfer is handled during 16-bit dma transfers. this mode is not used if byte control is selected via busmd 1:0 inputs and bso (byte select order) bit in the cntlreg2. this mode has no affect during 8-bit dma transfers and on transfers on the scsi bus. when the lbtm bit is set the dreq signal will not be asserted for the last byte, instead the host will read or write the last byte from or to the fifo. when the lbtm bit is reset the dreq signal will be asserted for the last byte and the following 16-bit dma transfer will contain the last byte on the lower bus. if the transfer is a dma read the upper bus will be all ones. the lbtm bit is reset by hard or soft reset. cntlreg3 C bit 1 C mdm C modify dma mode the mdm bit is used to modify the timing of the dack signal with respect to the dmard and dmawr signals. the mdm bit is used in conjunction with the burst size 8 (bs8) bit in the cntlreg3. both bits have to be set for proper operation. when the mdm bit is set and the device is in a dma read or write mode the dack signal will remain asserted while the data is strobed by the dmard or dmawr sig- nals. in the dma read mode when busmd 1:0 = 11 the dack signal will toggle for every dma read. when the mdm bit is reset and the device is in a dma read or write mode the dack signal will toggle every time the data is strobed by the dmard or dmawr signals.
p r e l i m i n a r y amd 32 am53c94/AM53C96 cntlreg3 C bit 0 C bs8 C burst size 8 the bs8 bit is used to modify the timing of the dreq signal with respect to the dmard and dmawr signals. the bs8 bit is used in conjunction with the modify dma mode (mdm) bit in the cntlreg3. both bits have to be set for proper operation. when the bs8 bit is set the device delays the assertion of the dreq signal until 8 bytes or 4 words transfer is possible. when the bs8 bit is set and the device is in a dma write mode the dreq signal will be asserted only when 8 byte locations are available for writing. in the dma read mode the dreq signal will go active under the following circumstances: at the end of a transfer, n in the target mode, C when the transfer is complete or C when the atn signal is active n in the initiator mode, C when the current transfer register is decremented to zero or C after any phase change in the middle of a transfer n in the initiator mode, C when the last 8 bytes of the fifo are full C during synchronous data-in transfer when the event transfer count register is greater than 7 and the last 8 bytes of the fifo are full. when the bs8 bit is reset and the device is in a dma read or write mode the dreq signal will toggle every time the data is strobed by the dmard or dmawr signals. using bit 0 (bs8) and bit 1 (mdm) of control register 3, one can enable the different combination modes shown in the table below. maximum (mdm) (bs8) function synchronous bit 1 bit 0 offset 0 0 normal dma mode 15 0 1 burst size 8 mode 7 1 0 reserved C 1 1 modified dma mode 15 data alignment register (0fh) write 16506c-33 the data alignment register (dalreg) is used if the first byte of a 16-bit dma transfer from the scsi bus to the host processor is misaligned. prior to issuing an in- formation transfer command, the host processor must set the data alignment enable (dae) bit in the cntlreg2. dalreg C bits 7:0 C da 7:0 C data alignment 7:0
p r e l i m i n a r y amd 33 am53c94/AM53C96 commands the device commands can be broadly divided into two categories, dma commands and non-dma commands. dma commands are those which cause data movement between the host memory and the scsi bus while non- dma commands are those that cause data movement between the device fifo and the scsi bus. the msb of the command byte differentiate the dma from the non- dma commands. summary of commands non- dma dma mode mode initiator commands information transfer 10 90 initiator command complete steps 11 91 message accepted 12 C transfer pad bytes 18 98 set atn 1a C reset atn 1b C target commands send message 20 a0 send status 21 a1 send data 22 a2 disconnect steps 23 a3 terminate steps 24 a4 target command complete steps 25 a5 disconnect 27 a7 receive message 28 a8 receive command steps 29 a9 receive data 2a aa receive command steps 2b ab target abort dma 04 84 non- dma dma mode mode idle state commands reselect steps 40 c0 select without atn steps 41 c1 select with atn steps 42 c2 select with atn and stop steps 43 c3 enable selection/reselection 44 c4 disable selection/reselection 45 c5 select with atn3 46 c6 general commands no operation 00 80 clear fifo 01 81 reset device 02 82 reset scsi bus 03 83 command code (hex.) command code (hex.) command command
p r e l i m i n a r y amd 34 am53c94/AM53C96 command description initiator commands initiator commands are executed by the device when it is in the initiator mode. if the device is not in the initiator mode and an initiator command is received the device will ignore the command, generate an illegal command interrupt and clear the command register (cmdreg) 03h. information transfer command (command code 10h/90h) the information transfer command is used to transfer information bytes over the scsi bus. this command may be issued during any scsi information transfer phase. information transfer for synchronous data must use the dma mode. the device will continue to transfer information until it is terminated by any one of the following conditions: n the target changes the scsi bus phase before the expected number of bytes are transferred. the device clears the command register (cmdreg) 03h, and generates a service interrupt when the target asserts req . n transfer is successfully complete. if the phase is message out, the device deasserts atn before asserting ack for the last byte of the message. when the target asserts req , a service interrupt is generated. n in the message in phase when the device receives the last byte. the device keeps the ack signal asserted and generates a successful operation interrupt. during synchronous data transfers the target may send up to the maximum synchronous threshold number of req pulses to the initiator. if it is the synchronous data- in phase then the target sends the data and the req pulses. these bytes are stored by the initiator in the fifo as they are received. information transfer command when issued during the following scsi phases and terminating in synchronous data phases, is handled as described below: n message in/status phase C when a phase change to synchronous data-in or synchronous data-out is detected by the device, the command register (cmdreg) 03h is cleared and the dma interface is disabled to disallow any transfer of data phase bytes. if the phase change is to synchronous data-in and bad parity is detected on the data bytes coming in, it is not reported since the status register (statreg) 04h will report the status of the command just completed. the parity error flag and the atn signal will be asserted when the transfer information command begins execution. n message out/command phase C when a phase change to synchronous data-in or synchronous data-out is detected by the device, the command register (cmdreg) 03h is cleared and the dma interface is disabled to allow any transfer of data phase bytes. if the phase change is to synchronous data-in and bad parity is detected on the data bytes coming in, it is not reported since the status register (statreg) 04h will report the status of the command just completed. the parity error flag and the atn signal will be asserted when the transfer information command begins execution. the fifo register29 (ffreg) 02h will be latched and will remain in that condition until the next command begins execution. the value in the ffreg indicates the number of bytes in the fifo when the phase changed to synchronous data-in. these bytes are cleared from the fifo, which now contains only the incoming data bytes. n in the synchronous data-out phase, the threshold counter is incremented as req pulses are received. the transfer is completed when the fifo is empty and the current transfer count register (ctcreg) 00hC01h is zero. the threshold counter will not be zero. n in the synchronous data-in phase, the current transfer count register (ctcreg) is decre- mented as bytes are read from the fifo rather than being decremented when the bytes are being written to the fifo. the transfer is completed when current transfer count register (ctcreg) is zero but the fifo may not be empty. initiator command complete steps (command code 11h/91h) the initiator command complete steps command is normally issued when the scsi bus is in the status in phase. one status byte followed by one message byte is transferred if this command completes normally. after receiving the message byte the device will keep the ack signal asserted to allow the initiator to examine the message and assert the atn signal if it is unacceptable. the command terminates early if the target does not switch to the message in phase or if the target discon- nects from the scsi bus. message accepted command (command code 12h) the message accepted command is used to release the ack signal. this command is normally used to com- plete a message in handshake. upon execution of this command the device generates a service request inter- rupt after req is asserted by the target.
p r e l i m i n a r y amd 35 am53c94/AM53C96 after the device has received the last byte of message, it keeps the ack signal asserted. this allows the device to either accept or reject the message. to accept the message, message accepted command is issued. to reject the message the atn signal must be asserted (with the help of the set atn command) before issuing the message accepted command. in either case the message accepted command has to be issued to re- lease the ack signal. transfer pad bytes command (command code 18h/98h) the transfer pad bytes command is used to recover from an error condition. this command is similar to the information transfer command, only the information bytes consists of null data. it is used when the target ex- pects more data bytes than the initiator has to send. it is also used when the initiator receives more information than it expected from the target. when sending data to the scsi bus, the fifo is loaded with null bytes and these bytes are sent out to the scsi bus. dma has to be enabled when pad bytes are trans- ferred to the scsi bus. no actual dma requests are made but the device uses the current transfer count register (ctcreg) 00hC01h to terminate the transfer. when receiving data from the scsi bus, the device will receive the pad bytes and place them on the top of the fifo and unload them from the bottom of the fifo. the command terminates under the same condition as the information transfer command, only the device does not keep the ack signal asserted during the last byte of the message in phase. if this command termi- nates prematurely, due to a disconnect or a phase change, before the ctcreg decrements to zero, the fifo may contain residual pad bytes. set atn command (command code 1ah) the set atn command is used to drive the atn signal active on the scsi bus. an interrupt is not generated at the end of this command. the atn signal is deasserted before asserting the ack signal during the last byte of the message out phase. note: the atn signal is asserted by the device without this command in the following cases: n if any select with atn command is issued and the arbitration is won. n an initiator needs the targets attention to send a message. the atn signal is asserted before deas- serting the ack signal. reset atn command (command code 1bh) the reset atn command is used to deassert the atn signal on the scsi bus. an interrupt is not generated at the end of this command. this command is used only when interfacing with devices that do not support the common command set (ccs). these older devices do not deassert their atn signal automatically on the last byte of the message out phase. this device does deas- sert its atn signal automatically on the last byte of the message out phase. target commands target commands are executed by the device when it is in the target mode. if the device is not in the target mode and a target command is received the device will ignore the command, generate an illegal command interrupt and clear the command register (cmdreg) 03h. a scsi bus reset during any target command will cause the device to abort the command sequence , flag a scsi bus reset interrupt (if the interrupt is enabled) and dis- connect from the scsi bus. normal or successful completion of a target command will cause a successful operation interrupt to be flagged. if the atn signal is asserted during a target command sequence the service request bit is asserted in the interrupt status register (instreg) 05h. if the atn signal is asserted when the device is in an idle state a service request interrupt will be generated, the suc- cessful operation bit in the instreg will be reset and the cmdreg cleared. send message command (command code 20h/a0h) the send message command is used by the target to inform the initiator to receive a message. the scsi bus phase lines are set to the message in phase and mes- sage bytes are transferred from the device fifo to the buffer memory. send status command (command code 21h/a1h) the send status command is used by the target to in- form the initiator to receive status information. the scsi bus phase lines are set to the status phase and status bytes are transferred from the target device to the initia- tor device. send data command (command code 22h/a2h) the send data command is used by the target to inform the initiator to receive data bytes. the scsi bus phase lines are set to the data-in phase and data bytes are transferred from the target device to the initiator device. disconnect steps command (command code 23h/a3h) the disconnect steps command is used by the target to disconnect from the scsi bus. this command consists of two steps. the first step consists of sending two bytes of the save data pointers commands by the target in the message in phase. in the second step the target discon- nects from the scsi bus. successful operation and dis- connected bits are set in the interrupt status register (instreg) 05h upon command completion. if atn sig- nal is asserted by the initiator then successful operation and service request bits are set in the instreg, the cmdreg is cleared and disconnect steps command terminates without disconnecting.
p r e l i m i n a r y amd 36 am53c94/AM53C96 terminate steps command (command code 24h/a4h) the terminate steps command is used by the target to disconnect from the scsi bus. this command consists of three steps. the first step consists of sending one status byte by the target in the status phase. the sec- ond step consists of sending one message byte by the target in the message in phase. as the third step the tar- get disconnects from the scsi bus. successful opera- tion and disconnected bits are set in the interrupt status register (instreg) 05h upon command completion. if atn signal is asserted by the initiator then successful operation and service request bits are set in the in- streg, the cmdreg is cleared and terminate steps command terminates without disconnecting. target command complete steps command (command code 25h/a5h) the target command complete steps command is used by the target to inform the initiator of a linked com- mand completion. this command consists of two steps. the first step consists of sending one status byte by the target in the status phase. the second step consists of sending one message byte by the target in the message in phase. the successful operation bit is set in the in- terrupt status register (instreg) 05h upon command completion. if atn signal is asserted by the initiator then successful operation and service request bits are set in the instreg, the cmdreg is cleared and target command complete steps command terminates prematurely. disconnect command (command code 27h/a7h) the disconnect command is used by the target to dis- connect from the scsi bus. all scsi bus signals except rstc are released and the device returns to the dis- connected state. the rstc signal is driven active for about 25 micro seconds (depending on clock frequency and clock factor). interrupt is not generated to the micro- processor. receive message steps command (command code 28h a8h) the receive message steps command is used by the target to request message bytes from the initiator. dur- ing this command the target receives the message bytes from the initiator while the scsi bus is in the mes- sage out phase. the successful operation bit is set in the interrupt status register (instreg) 05h upon command completion. if atn signal is asserted by the initiator then successful operation and service re- quest bits are set in the instreg, the cmdreg is cleared. if a parity error is detected, the device ignores the received message bytes until atn signal is as- serted, the successful operation bit is set in the in- streg, and the cmdreg is cleared. receive commands command (command code 29h/a9h) the receive commands command is used by the tar- get to request the initiator for command bytes. during this command the target receives the command bytes from the initiator while the scsi bus is in the command phase. the successful operation bit is set in the inter- rupt status register (instreg) 05h upon command completion. if atn signal is asserted by the initiator then successful operation and service request bits are set in the instreg, the cmdreg is cleared and the com- mand terminates prematurely. if a parity error is de- tected, the device continues to receive command bytes until the transfer is complete if the abort on command/ data parity error (acdpe) bit in the control register (cntlreg2) 0bh is reset. if the acdpe bit is set, the command is terminated immediately. the parity error (pe) bit in the status register (statreg) 04h is set and cmdreg is cleared. receive data command (command code 2ah/aah) the receive data command is used by the target to re- quest the initiator for data bytes. during this command the target receives the data bytes from the initiator while the scsi bus is in the data-out phase. the successful operation bit is set in the interrupt status register (in- streg) 05h upon command completion. if atn signal is asserted by the initiator then successful operation and service request bits are set in the instreg, the cmdreg is cleared and the command terminates pre- maturely. if a parity error is detected, the device contin- ues to receive data bytes until the transfer is complete if the abort on command/data parity error (acdpe) bit in the control register (cntlreg2) 0bh is reset. if the acdpe bit is set, the command is terminated immedi- ately. the parity error (pe) bit in the status register (statreg) 04h is set and cmdreg is cleared. receive command steps command (command code 2bh/abh) the receive command steps command is used by the target to request the initiator for command information bytes. during this command the target receives the command information bytes from the initiator while the scsi bus is in the command phase. the target device determines the command byte length from the first command byte. if an unknown length is re- ceived, the start transfer count register (stcreg) 00hC01h is loaded with 5 and the group code valid (gcv) bit in the status register (statreg) 04h is re- set. if a valid length is received, the stcreg is loaded with the appropriate value and the gcv bit in the statreg is set. if atn signal is asserted by the initia- tor then the service request bit is set in the instreg, and the cmdreg is cleared if a parity error is detected, the command is terminated prematurely and the cmdreg is cleared. dma stop command (command code 04h/84h) the dma stop command is used by the target to allow the microprocessor to discontinue data transfers due to a lack of activity on the dma channel. this command is executed from the top of the command queue. if there is a queued command waiting execution, it will be over- written and the illegal operation error (ioe) bit in the
p r e l i m i n a r y amd 37 am53c94/AM53C96 status register (statreg) 04h will be set. this com- mand is cleared from the command queue once it is decoded. caution must be exercised when using this command. the dma stop command can be used only during a dma target send data command or dma target re- ceive data command execution. in both cases the dma controller has to be in the idle state. during a dma target send data command the fifo has to be empty or the current fifo (cf 4:0) bits in the current fifo/internal state register (cfisreg) 07h are zero. during a dma synchronous target receive data com- mand the current transfer count register (ctcreg) 00C01h is zero, which is indicated by the count to zero (ctz) bit of the status register (statreg) 04h. or when the synchronous offset register (sofreg) 07h has reached its maximum value which is indicated by the synchronous offset flag (sof) bit of the internal state register (isreg) 06h. during a dma asynchronous target receive data command the fifo is full which is indicated by the cur- rent fifo (cf 4:0) bits in the current fifo/internal state register (cfisreg) 07h being all high or current transfer count register (ctcreg) 00C01h is zero, which is indicated by the count to zero (ctz) bit of the status register (statreg) 04h. idle state commands the idle state commands can be issued to the device only when the device is disconnected from the scsi bus. if these commands are issued to the device when it is logically connected to the scsi bus, the commands are ignored, and the device will generate an illegal com- mand interrupt and clear the command register (cmdreg) 03h. reselect steps command (command code 40h/c0h) the reselect steps command is used by the target de- vice to reselect an initiator device. when this command is issued the device arbitrates for the control of the scsi bus. if the device wins arbitration, it reselects the initia- tor device and transfers a single byte identify message. before issuing this command the scsi timeout regis- ter (stimreg) 05h, the control register one (cntlreg1) 08h and the scsi destination id regis- ter (sdidreg) 04h must be set to the proper values. if dma is enabled, the start transfer count register (stcreg) 00hC01h must be set to one. if dma is not enabled, the single byte identify message must be loaded into the fifo before issuing this command. this command will be terminated early if the scsi timeout register times out. this command also resets the inter- nal state register (isreg) 06h. select without atn steps command (command code 41h/c1h) the select without atn steps command is used by the initiator to select a target. when this command is issued the device arbitrates for the control of the scsi bus. when the device wins arbitration, it selects the target device and transfers the command descriptor block (cdb). before issuing this command the scsi timeout register (stimreg) 05h, the control register one (cntlreg1) 08h and the scsi destination id regis- ter (sdidreg) 04h must be set to the proper values. if dma is enabled, the start transfer count register (stcreg) 00hC01h must be set to the total length of the command. if dma is not enabled, the data must be loaded into the fifo before issuing this command. this command will be terminated early if the scsi timeout register times out or if the target does not go to the command phase following the selection phase or if the target exits the command phase early. select with atn steps command (command code 42h/c2h) the select with atn steps command is used by the in- itiator to select a target. when this command is issued the device arbitrates for the control of the scsi bus. when the device wins arbitration, it selects the target device with the atn signal asserted and transfers the command descriptor block (cdb) and a one byte mes- sage. before issuing this command the scsi timeout register (stimreg) 05h, the control register one (cntlreg1) 08h and the scsi destination id regis- ter (sdidreg) 04h must be set to the proper values. if dma is enabled, the start transfer count register (stcreg) 00hC01h must be set to the total length of the command. if dma is not enabled, the data must be loaded into the fifo before issuing this command. this command will be terminated early in the following situ- ations: n the scsi timeout register times out n the target does not go to the message out phase following the selection phase n the target exits the message phase early n the target does not go to the command phase following the selection phase n the target exits the command phase early. select with ant and stop steps command (command code 43h/c3h) the select with atn and stop steps command is used by the initiator to select a target. when this command is issued the device arbitrates for the control of the scsi bus. when the device wins arbitration, it selects the tar- get device with the atn signal asserted and transfers the command descriptor block (cdb) and stops after one message byte is sent, but the atn signal is not
p r e l i m i n a r y amd 38 am53c94/AM53C96 deasserted at the end of the command which allows the initiator to send other messages after the id message is sent out. before issuing this command the scsi timeout register (stimreg) 05h, the control register one (cntlreg1) 08h and the scsi destination id register (sdidreg) 04h must be set to the proper val- ues. this command will be terminated early if the scsi timeout register times out or if the target does not go to the message out phase following the selection phase. enable selection/reselection command (command code 44h/c4h) the enable selection/reselection command is used by the target to respond to a bus-initiated reselection. upon disconnecting from the bus the selection/reselection circuit is automatically disabled by device. this circuit has to be enabled for the device to respond to subse- quent reselection attempts and the enable selection/ reselection command is issued to do that. this com- mand is normally issued within 250 ms (select/reselect timeout) after the device disconnects from the bus. if dma is enabled the device loads the received data to the buffer memory, but if the dma is disabled, the re- ceived data stays in the fifo. disable selection/reselection command (command code 45h/c5h) the disable selection/reselection command is used by the target to disable response to a bus-initiated reselection. when this command is issued before a bus initiated selection or reselection is initiated, it resets the internal mode bits previously set by the enable selec- tion/reselection command. the device also generates a function complete interrupt to the processor. if how- ever, this command is issued after a bus initiated selec- tion/reselection has already begun the command is ig- nored since the command register is held reset and all incoming commands are ignored. the device generates a selected or reselected interrupt when the sequence is complete. select with atn3 steps command (command code 46h/c6h) the select with atn3 steps command is used by the initiator to select a target. this command is similar to the select with atn steps command, except that it sends exactly three message bytes. when this command is issued the device arbitrates for the control of the scsi bus. when the device wins arbitration, it selects the target device with the atn signal asserted and transfers the command descriptor block (cdb) and three message bytes. before issuing this command the scsi timeout register (stimreg) 05h, the control register one (cntlreg1) 08h and the scsi destination id register (sdidreg) 04h must be set to the proper values. if dma is enabled, the start transfer count register (stcreg) 00hC01h must be set to the total length of the command. if dma is not enabled, the data must be loaded into the fifo before issuing this command. this command will be terminated early in the following situations: n the scsi timeout register times out n the target does not go to the message out phase following the selection phase n the target exits the message phase early n the target does not go to the command phase following the selection phase n the target exits the command phase early. general commands no operation command (command code 00h/80h) the no operation command is used to perform no op- eration and no interrupt is generated at the end of this command. this command is issued after the reset de- vice command to enable the command register. a no operation command in the dma mode may be used to verify the contents of the start transfer count register (stcreg) 00h C 01h. after the stcreg is loaded with the transfer count and a no operation command is is- sued, reading the current transfer count register (ctcreg) 00hC01h will give the transfer count value. clear fifo command (command code 01h/81h) the clear fifo command is used to initialize the fifo to the empty condition. the current fifo register (cfisreg) 07h reflects the empty fifo status and the bottom of the fifo is set to zero. no interrupt is gener- ated at the end of this command. reset device command (command code 02h/82h) the reset device command immediately stops any de- vice operation and resets all the functions of the device. it returns the device to the disconnected state and it also generates a hard reset. the reset device command re- mains on the top of the command register fifo hold- ing the device in the reset state until the no operation command is loaded. the no operation command serves to enable the command register. reset scsi bus command (command code 03h/83h) the reset scsi bus command is used to assert the rstc signal for approximately 25 ms. this command causes the device to go to the disconnected state. no interrupt is generated upon command completion. a scsi reset interrupt is however generated upon com- mand completion if the interrupt is not disabled in the control register one (cntlreg1) 08h.
p r e l i m i n a r y amd 39 am53c94/AM53C96 absolute maximum ratings storage temperature C65 c to +150 c . . . . . . . . . . . ambient temperature under bias C55 c to +125 c . v dd C0.5 v to +7.0 v . . . . . . . . . . . . . . . . . . . . . . . . . dc voltage applied to any pin C0.5 to (v dd +0.5) v . input static discharge protection 4000 v pin to pin . . (human body model: 100 pf at 1.5k w ) stresses above those listed under absolute maximum rat- ings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maxi- mum ratings for extended periods may affect device reliability. operating ranges commercial devices ambient temperature (t a )0 c to +70 c . . . . . . . supply voltage (v dd ) +4.75 v to +5.25 v . . . . . . . operating ranges define those limits between which the func- tionality of the device is guaranteed.
p r e l i m i n a r y amd 40 am53c94/AM53C96 dc operating characteristics i dds static supply current v dd max 4.0 ma i ddd dynamic supply current v dd max 35 ma i lu latch up current all i/o v lu 10 v C 100 +100 ma c capacitance all pins 10 pf v ih input high voltage all scsi inputs 2.0 v dd + 0.5 v v il input low voltage all scsi inputs v ss C 0.5 0.8 v v ihst input hysterisis all scsi inputs 4.75 v < v dd < 5.25 v 300 mv v oh output high voltage sd 7C0 , sd p i oh = C 2 ma 2.4 v dd v v sol1 scsi output low voltage sd 7C0 , sd p i ol = 4 ma v ss 0.4 v v sol2 scsi output low voltage sdc 7C0 , sdc p , i ol = 48 ma v ss 0.5 v msg , c/d , i/o , atn , rstc , selc , bsyc , ackc and reqc i il input low leakage 0.0 v < v in < 2.7 v C10 +10 m a i ih input high leakage 2.7 v < v in < v dd C10 +10 m a i oz high impedance leakage 0 v < v out < v dd C10 +10 m a v ih input high voltage 2.0 v dd + 0.5 v v il input low voltage v ss C 0.5 0.8 v v oh output high voltage dma 15C0, i oh = C 2 ma 2.4 v dd v dmap 1C0 and ad 7C0 v ol output low voltage dma 15C0, i ol = 4 ma v ss 0.4 v dmap 1C0 and ad 7C0 i il input low leakage dma 15C0, v in = v il C 400 +10 m a dmap 1C0 and ad 7C0 i ih input high leakage dma 15C0, v in = v ih C10 +10 m a dmap 1C0 and ad 7C0 i oz high impedance leakage 0 v < v out < v dd C100 400 m a v oh output high voltage dreq, isel, i oh = C 2 ma 2.4 v dd v tsel v ol output low voltage dreq, isel, i ol = 4 ma v ss 0.4 v tsel i oz high impedance leakage 0 v < v out < v dd C10 +10 m a parameter symbol parameter description pin names test conditions min max unit scsi pins bidirectional pins output pins
p r e l i m i n a r y amd 41 am53c94/AM53C96 dc operating characteristics (continued) parameter symbol parameter description pin names test conditions min max unit v ih input high voltage a 3-0, cs , rd . wr , 2.0 v cc + 0.5 v dmawr , clk, busmd 1-0, dack , reset, and dfmode v il input low voltage a 3-0, cs , rd . wr ,v ss + 0.5 0.8 v dmawr , clk, busmd 1-0, dack , reset, and dfmode i il input low leakage a 3-0, cs , rd . wr , C10 +10 m a dmawr , clk, busmd 1-0, dack , reset, and dfmode i ih input high voltage a 3-0, cs , rd . wr , C10 +10 m a dmawr , clk, busmd 1-0, dack , reset, and dfmode input pins v in = v ih v in = v il v t i ol i oh c l 0 v from output under test 16505c-34 switching test circuit switching test waveforms true data outputs ad 7C0, dma 15C0, dmap1C0 all inputs 1.5 v 3.0 v 0.0 v hi-z outputs ad 7C0, dma 15C0, dmap1C0 0.8 v all open drain outputs 1.5 v all other outputs v oh v ol v ol +0.3 v v ol v ol v oh 1.5 v v oh C0.3 v 1.5 v 16505c-35 1.5 v 2.0 v 0.8 v
p r e l i m i n a r y amd 42 am53c94/AM53C96 key to switching waveforms ks000010 must be steady may change from h to l may change from l to h does not apply dont care, any change permitted will be steady will be changing from h to l will be changing from l to h changing, state unknown center line is high- impedance off state waveform inputs outputs
p r e l i m i n a r y amd 43 am53c94/AM53C96 parameter no. symbol parameter description test conditions min max unit 1t pwl clock pulse width low 14.58 ns 2t cp clock period 40 100 ns 3t l synchronization latency 54.58 185.42 ns (parameter 2 + parameter 1) 4t pwh clock pulse width high 14.58 ns reset parameter no. symbol parameter description test conditions min max unit reset input 5t pwh reset pulse width high 500 ns clk clock input 3 5 1 4 2 note: clock frequency range = 10 to 25 mhz for asynchronous scsi bus = 12 to 25 mhz for synchronous scsi bus 16505c-36 16505c-37 note: there is a one-to-one relationship between every amd and ncr parameter (refer to appendix b).
p r e l i m i n a r y amd 44 am53c94/AM53C96 6t s int to rd set up time 0 ns 7t pd rd to int delay 0 100 ns 8t pwl rd pulse width low 50 ns 9t pd rd to int delay t l C t pd ns parameter no. symbol parameter description test conditions min max unit int rd interrupt output 68 9 7 16505c-38 note: there is a one-to-one relationship between every amd and ncr parameter (refer to appendix b).
p r e l i m i n a r y amd 45 am53c94/AM53C96 parameter no. symbol parameter description test conditions min max unit 10 t s address to cs set up time 0 ns 11 t h address to cs hold time 50 ns 12 t s cs to rd set up time 0 ns 13 t pd cs to data valid delay 90 ns 14 t pwl rd pulse width low 50 ns 15 t pd rd to data valid delay 50 ns 16 t h rd to cs hold time 0 ns 17 t z rd to data high impedance 40 ns 18 t h rd to data hold time 2 ns 19 t pwh cs pulse width high 40 ns 20 t s cs to wr set up time 0 ns 21 t pwl wr pulse width low 40 ns 22 t s data to wr set up time 15 ns 23 t h wr to cs hold time 0 ns 24 t s wr to cs set up time 60 ns 25 t pwh wr pulse width high 60 ns 26 t h data to wr hold time 0 ns cs rd wr ad 7C0 dma 7C0 dmap 0 a3C0 register read/write with non-multiplexed address data bus 10 11 10 11 19 19 23 24 16 12 14 20 21 25 22 26 15 13 18 17 16505c-39 note: there is a one-to-one relationship between every amd and ncr parameter (refer to appendix b).
p r e l i m i n a r y amd 46 am53c94/AM53C96 31 27 t pwh ale pulse width high 20 ns 28 t s address to ale set up time 10 ns 29 t h address to ale hold time 10 ns 30 t s ale to cs set up time 10 ns 31 t pd cs to data valid delay 90 ns 32 t s cs to rd set up time 0 ns 33 t pd rd to data valid delay 50 ns 34 t pwl rd pulse width low 50 ns 35 t h rd to data hold time 2 ns 36 t h rd to cs hold time 0 ns 37 t z rd to data high impedance 40 ns 38 t s cs to ale set up time 50 ns 39 t s cs to wr set up time 0 ns 40 t pwl wr pulse width low 40 ns 41 t s data to wr set up time 15 ns 42 t s wr to ale set up time 50 ns 43 t h data to wr hold time 0 ns 44 t h wr to cs hold time 0 ns parameter no. symbol parameter description test conditions min max unit cs rd wr ad 7C0 al register read/write with multiplexed address data bus 28 29 27 30 38 32 34 36 33 35 39 40 44 41 43 27 28 29 30 address data address data 37 42 16506c-40 note: there is a one-to-one relationship between every amd and ncr parameter (refer to appendix b).
p r e l i m i n a r y amd 47 am53c94/AM53C96 45 t pd dack to dreq valid delay 38 ns 46 t p dack to dack period 100 ns 47 t pwl dack pulse width low 60 ns 48 t pd dack to data valid delay 41 ns 49 t pd dack to dreq valid delay 40 ns 50 t p dack to dack period t 3 +50Ct 51 ns 51 t pwh dack pulse width high 12 ns 52 t z dack to data high impedance 40 ns 53 t h dack to data hold time 2 ns 54 t s dack to dmawr set up time 0 ns 55 t pwl dmawr pulse width low 50 ns 56 t s data to dmawr set up time 15 ns 57 t h dmawr to dack hold time 0 ns 58 t pwh dmawr pulse width high 40 ns 59 t h data to dmawr hold time 0 ns parameter no. symbol parameter description test conditions min max unit note: there is a one-to-one relationship between every amd and ncr parameter (refer to appendix b). dma read without byte control 45 49 46 47 67 51 48 53 52 50 dreq dack dma 15C0 dmap 1C0 49 45 51 47 dma write without byte control 45 49 46 47 51 55 57 54 56 59 50 58 52 49 45 47 48 53 51 dma 15C0 dmap 1C0 dreq dack dmawr 16506c-41 16506c-42
p r e l i m i n a r y amd 48 am53c94/AM53C96 dma read with byte control dma 15C0 dmap 1C0 dreq dack dmard as 0 bhe 60 71 61 62 73 64 67 63 68 66 72 70 69 69 70 71 60 61 73 62 65 66 dma write with byte control 60 71 61 62 73 75 78 72 74 76 79 77 81 80 dreq dack as 0 bhe dmawr dma 15C0 dmap 1C0 71 60 61 73 62 16506c-53 16506c-52
p r e l i m i n a r y amd 49 am53c94/AM53C96 60 t pd dack to dreq valid delay 38 ns 61 t p dack to dack period 100 ns 62 t pwl dack pulse width low 60 ns 63 t s dack to dmard set up time 0 ns 64 t s bhe, as0 to dmard set up time 20 ns 65 t pwl dmard pulse width low 60 ns 66 t pd dmard to data valid delay 51 ns 67 t h bhe, as0 to dmard hold time 20 ns 68 t h dmard to dack hold time 0 ns 69 t z dmard to data high impedance 40 ns 70 t h dmard to data hold time 2 ns 71 t pd dack to dreq valid delay 40 ns 72 t p dack to dack period 100 ns 73 t pwh dack pulse width high 12 ns 74 t s dack to dmawr set up time 0 ns 75 t s bhe, as0 to dmawr set up time 20 ns 76 t pwl dmawr pulse width low 50 ns 77 t s data to dmawr set up time 15 ns 78 t h bhe, as0 to dmawr hold time 20 ns 79 t h dmawr to dack hold time 0 ns 80 t pwh dmawr pulse width high 40 ns 81 t h data to dmawr hold time 0 ns parameter no. symbol parameter description test conditions min max unit note: there is a one-to-one relationship between every amd and ncr parameter (refer to appendix b).
p r e l i m i n a r y amd 50 am53c94/AM53C96 dack dreq dreq dack dma 15C0 dmap 1C0 dma 15C0 dmap 1C0 dmard dmawr burst dma read without byte control burst dma write without byte control 93 93 82 83 83 94 94 87 97 90 101 84 95 85 96 88 98 89 99 86 92 100 91 102 16506c-43 16506c-44 82
p r e l i m i n a r y amd 51 am53c94/AM53C96 82 t pd dack to dreq valid delay 45 ns 83 t pwl dack pulse width low 100 ns 84 t s dack to dmard set up time 0 ns 85 t p dmard to dmard period 130 ns 86 t pd dmard to data valid delay 70 ns 87 t pwh dmard pulse width high 60 ns 88 t pwl dmard pulse width low 70 ns 89 t p dmard to dmard period t 3 + 50 ns 90 t pd dmard to dreq valid delay 140 ns 91 t z dmard to data high impedance 50 ns 92 t h dmard to data hold time 2 ns 93 t pd dack to dreq valid delay 40 ns 94 t pwh dack pulse width high 60 ns 95 t s dack to dmawr set up time 0 ns 96 t p dmawr to dmawr period 160 ns 97 t pwh dmawr pulse width high 60 ns 98 t pwl dmawr pulse width low 100 ns 99 t p dmawr to dmawr period t 3 + 50 ns 100 t s data to dmawr set up time 15 ns 101 t pd dmawr to dreq valid delay 140 ns 102 t h data to dmawr hold time 0 ns parameter no. symbol parameter description test conditions min max unit note: there is a one-to-one relationship between every amd and ncr parameter (refer to appendix b).
p r e l i m i n a r y amd 52 am53c94/AM53C96 burst dma write with byte control burst dma read with byte control 116 116 103 103 104 104 117 117 121 109 125 113 118 106 120 107 122 110 124 112 108 127 115 126 114 dreq dack dma 15C0 dmap 1C0 dmawr as 0 bhe dreq dack dma 15C0 dmap 1C0 dmard as 0 bhe 119 105 123 111 16506c-45 16506c-46
p r e l i m i n a r y amd 53 am53c94/AM53C96 103 t pd dack to dreq valid delay 45 ns 104 t pwl dack pulse width low 100 ns 105 t s bhe, as0 to dmard set up time 20 ns 106 t s dack to dmard set up time 0 ns 107 t p dmard to dmard period 130 ns 108 t pd dmard to data valid delay 70 ns 109 t pwh dmard pulse width high 60 ns 110 t pwl dmard pulse width low 70 ns 111 t h bhe, as0 to dmard hold time 20 ns 112 t p dmard to dmard period t 3 + 50 ns 113 t pd dmard to dreq valid delay 140 ns 114 t z dmard to data high impedance 50 ns 115 t h dmard to data hold time 2 ns 116 t pd dack to dreq valid delay 50 ns 117 t pwh dack pulse width high 60 ns 118 t s dack to dmawr set up time 0 ns 119 t s bhe, as0 to dmawr set up time 20 ns 120 t p dmawr to dmawr period 160 ns 121 t pwh dmawr pulse width high 60 ns 122 t pwl dmawr pulse width low 100 ns 123 t h bhe, as0 to dmawr hold time 20 ns 124 t p dmawr to dmawr period t 3 + 50 ns 125 t pd dmawr to dreq valid delay 140 ns 126 t h data to dmawr hold time 0 ns 127 t s data to dmawr set up time 15 ns parameter no. symbol parameter description test conditions min max unit note: there is a one-to-one relationship between every amd and ncr parameter (refer to appendix b).
p r e l i m i n a r y amd 54 am53c94/AM53C96 parameter no. symbol parameter description test conditions min max unit 132 t pd req to ackc delay 43 ns 133 t pd req to ackc delay 47 ns 128 t s data to ackc set up time 55 ns 129 t pd req to data delay 80 ns 130 t pd req to ackc delay 46 ns 131 t pd req to ackc delay 55 ns parameter no. symbol parameter description test conditions min max unit req ackc asynchronous initiator receive sdc 7C0 sdcp asynchronous initiator send 129 132 133 req ackc 128 130 131 16505c-47 16505c-48 note: there is a one-to-one relationship between every amd and ncr parameter (refer to appendix b).
p r e l i m i n a r y amd 55 am53c94/AM53C96 parameter no. symbol parameter description test conditions min max unit 138 t pd ack to reqc delay 60 ns 139 t pd ack to reqc delay 45 ns 134 t s data to reqc set up time 55 ns 135 t pd ack to data delay 78 ns 136 t pd ack to reqc delay 60 ns 137 t pd ack to reqc delay 45 ns parameter no. symbol parameter description test conditions min max unit ack reqc asynchronous target receive sdc 7C0 sdcp asynchronous target send 135 138 139 ack reqc 134 136 137 16505c-49 16505c-50 note: there is a one-to-one relationship between every amd and ncr parameter (refer to appendix b).
p r e l i m i n a r y amd 56 am53c94/AM53C96 140 t pd clk to data delay 15* 90 ns 141 t s ackc or reqc to data 55 ns set up time 142 t pd clk to ackc or reqc delay 13* 68 ns 143 t pd clk to ackc or reqc delay 17 70 ns parameter no. symbol parameter description test conditions min max unit synchronous initiator target transmit 140 reqc ackc sdc 7C0 sdcp clk 142 141 140 143 142 16505c-51 note: there is a one-to-one relationship between every amd and ncr parameter (refer to appendix b). * the minimum values have a wide range since they depend on the synchronization latency. the synchronization latency, in turn, depends on the operating frequency of the device.
p r e l i m i n a r y amd 57 am53c94/AM53C96 appendix a pin connection cross reference for am53c94 pin# amd ncr 1 dmap0 dbp0 2v ss v ss 3 dma8 db8 4 dma9 db9 5 dma10 db10 6 dma11 db11 7 dma12 db12 8 dma13 db13 9 dma14 db14 10 dma15 db15 11 dmap1 dbp1 12 sd 0 sdi0/ 13 sd 1 sdi1/ 14 sd 2 sdi2/ 15 sd 3 sdi3/ 16 sd 4 sdi4/ 17 sd 5 sdi5/ 18 sd 6 sdi6/ 19 sd 7 sdi7/ 20 sd p sdip/ 21 v dd v dd 22 v ss v ss 23 sdc 0 sdo0/ 24 sdc 1 sdo1/ 25 sdc 2 sdo2/ 26 sdc 3 sdo3/ 27 v ss v ss 28 sdc 4 sdo4/ 29 sdc 5 sdo5/ 30 sdc 6 sdo6/ 31 sdc 7 sdo7/ 32 sdc p sdop/ 33 v ss v ss 34 selc selo/ 35 bsyc bsyo/ 36 reqc reqo/ 37 ackc acko/ 38 v ss v ss 39 msg msgio/ 40 c/d c/dio 41 i/o i/oio 42 atn atnio/ pin# amd ncr 43 rstc rsto/ 44 v ss v ss 45 sel seli/ 46 bsy bsyi/ 47 req reqi/ 48 ack acki/ 49 rst rsti/ 50 busmd 1 mode 1 51 busmd 0 mode 0 52 int int/ 53 reset reset 54 wr wr/ 55 rd rd/ 56 cs cs/ 57 aso [ao] a0Csa0 58 bhe [a1] a1Cbhe 59 dmard [a2] a2Cdbrd/ 60 ale [a3] a3Cale 61 clk clk 62 v dd v dd 63 ad0 pad0 64 ad1 pad1 65 ad2 pad2 66 ad3 pad3 67 v ss v ss 68 ad4 pad4 69 ad5 pad5 70 ad6 pad6 71 ad7 pad7 72 dreq dreq 73 dack dack/ 74 dmawr dbwr/ 75 v ss v ss 76 v ss v ss 77 dma0 db0 78 dma1 db1 79 dma2 db2 80 dma3 db3 81 dma4 db4 82 dma5 db5 83 dma6 db6 84 dma7 db7
p r e l i m i n a r y amd 58 am53c94/AM53C96 appendix a pin connection cross reference for AM53C96 pin# amd ncr 1 dack dack 2 dmawr dbwr/ 3nc nc 4 isel igs 5v ss v ss 6 tsel tgs 7v ss v ss 8 dma0 db0 9 dma1 db1 10 dma2 db2 11 dma3 db3 12 dma4 db4 13 dma5 db5 14 dma6 db6 15 dma7 db7 16 dmap0 dbp0 17 v ss v ss 18 v ss v ss 19 dma8 db8 20 dma9 db9 21 dma10 db10 22 dma11 db11 23 dma12 db12 24 dma13 db13 25 dma14 db14 26 dma15 db15 27 dmap1 dbpi 28 nc nc 29 sd 0 sdi0/ 30 sd 1 sdi1/ 31 sd 2 sdi2/ 32 sd 3 sdi3/ 33 sd 4 sdi4/ 34 sd 5 sdi5/ 35 sd 6 sdi6/ 36 sd 7 sdi7/ 37 sd p sdip/ 38 v dd v dd 39 nc nc 40 v ss v ss 41 v ss v ss 42 sdc 0 sdo0/ 43 sdc 1 sdo1/ 44 sdc 2 sdo2/ 45 sdc 3 sdo3/ 46 v ss v ss 47 v ss v ss 48 sdc 4 sdo4/ 49 sdc 5 sdo5/ 50 sdc 6 sdo6/ pin# amd ncr 51 sdc 7 sdo7/ 52 sdc p sdop/ 53 nc nc 54 v ss v ss 55 v ss v ss 56 selc selo/ 57 bsyc bsyo/ 58 reqc reqo/ 59 ackc acko/ 60 v ss v ss 61 v ss v ss 62 msg msgio/ 63 c/d c/dio 64 i/o i/oio 65 atn atnio/ 66 rstc rsto/ 67 v ss v ss 68 v ss v ss 69 sel seli/ 70 bsy bsyi/ 71 req reqi/ 72 ack acki/ 73 rst rsti/ 74 busmd 1 mode 1 75 busmd 0 mode 0 76 int int/ 77 reset reset 78 nc nc 79 wr wr/ 80 rd rd/ 81 cs cs/ 82 aso [a0] a0Csao 83 bhe [a1] a1Cbhe 84 dmard [a2] a2Cdbrd/ 85 ale [a3] a3Cale 86 clk clk 87 dfmode diffm/ 88 v dd v dd 89 nc nc 90 ad0 pad0 91 ad1 pad1 92 ad2 pad2 93 ad3 pad3 94 v ss v ss 95 v ss v ss 96 ad4 pad4 97 ad5 pad5 98 ad6 pad6 99 ad7 pad7 100 dreq dreq
p r e l i m i n a r y amd 59 am53c94/AM53C96 appendix b amd/ncr timing parameters cross reference amd parameter # t ch 4 t cl 1 t cp 2 t cs 3 t rst 5 t ir 6 t rd 8 t ri 7 t icy 9 t rdp1 10 t rdp2 11 t rdp3 19 t rdp4 13 t rdp5 12 t rdp6 14 t rdp7 16 t rdp8 15 t rdp9 (max) 17 t rdp9 (min) 18 t rdp10 20 t rdp11 21 t rdp12 23 t rdp13 22 t rdp14 26 t rdp15 24 t rdp16 25 t rmp1 28 t rmp2 29 t rmp3 27 t rmp4 30 t rmp5 31 t rmp6 38 t rmp7 32 t rmp8 34 t rmp9 36 t rmp10 33 t rmp11 (max) 37 t rmp11 (min) 35 t rmp12 39 t rmp13 40 t rmp14 44 t rmp15 41 t rmp16 43 t rmp17 42 t dnb1 45 t dnb2 49 t dnb3 51 t dnb4 47 amd parameter # t dnb5 46 t dnb6 50 t dnb7 48 t dnb8 (max) 52 t dnb8 (min) 53 t dnb9 54 t dnb10 55 t dnb11 57 t dnb12 56 t dnb13 59 t dnb14 58 t dbc1 60 t dbc2 71 t dbc3 73 t dbc4 62 t dbc5 61 t dbc6 72 t dbc7 64 t dbc8 67 t dbc9 63 t dbc10 65 t dbc11 68 t dbc12 66 t dbc13 (max) 69 t dbc13 (min) 70 t dbc14 75 t dbc15 78 t dbc16 74 t dbc17 76 t dbc18 79 t dbc19 77 t dbc20 81 t dbc21 80 t dan1 93 t dan2 82 t dan3 94 t dan4 83 t dan5 90 t dan6 84 t dan7 88 t dan8 87 t dan9 86 t dan10 (max) 91 t dan10 (min) 92 t dan11 85 t dan12 89 t dan13 101 t dan14 95 amd parameter # t dan15 98 t dan16 97 t dan17 100 t dan18 102 t dan19 96 t dan20 99 t dab1 116 t dab2 103 t dab3 117 t dab4 104 t dab5 113 t dab6 105 t dab7 111 t dab8 106 t dab9 110 t dab10 109 t dab11 108 t dab12 (max) 114 t dab12 (min) 115 t dab13 107 t dab14 112 t dab15 125 t dab16 119 t dab17 123 t dab18 118 t dab19 122 t dab20 121 t dab21 127 t dab22 126 t dab23 120 t dab24 124 t laxda 128 t laxah 130 t laxrd 129 t laxal 131 t larah 132 t laral 133 t taxdr 134 t taxrh 136 t taxad 135 t taxrl 137 t tarrh 138 t tarrl 139 t sxd 140 t sxral 142 t sxrah 143 t sxdsu 141 ncr symbol ncr symbol ncr symbol
p r e l i m i n a r y amd 60 am53c94/AM53C96 physical dimensions* pl 084 plastic leaded chip carrier (measured in inches) .050 ref .042 .048 1.150 1.156 1.185 1.195 1.150 1.156 1.185 1.195 .042 .056 .165 .180 .090 .130 .007 .013 1.000 ref .013 .021 1.090 1.130 .020 min .025 .045 09980b cg08 pl 084 8/14/92 c dc r top view side view .026 .032 * for reference only. bsc is an ansi standard for basic space centering.
p r e l i m i n a r y amd 61 am53c94/AM53C96 physical dimensions* pqr100 plastic quad flatpack trimmed and formed (measured in millimeters) 0.22 0.38 13.90 14.10 17.10 17.30 18.85 ref 19.90 20.10 23.00 23.40 0.65 ref pin 1 i.d. 12.35 ref 2.60 3.00 3.35 max 0.70 0.90 top view side view 15590d bx 45 9/6/91 sg pqj 100 (plastic quad flat pack; trimmed and formed) (measured in millimeters) 0.25 min
p r e l i m i n a r y amd 62 am53c94/AM53C96 physical dimensions* pqr100 molded carrier ring plastic quad flatpack (measured in millimeters) top view pin 1 i.d. 19.80 20.10 27.87 28.13 31.37 31.63 35.87 36.13 13.80 14.10 25.20 bsc 27.87 28.13 31.37 31.63 35.50 35.90 35.87 36.13 .65 nom .65 typ .65 pitch .45 typ 2.00 4.80 1.80 side view cb 48 6/25/92 sg 0.22 0.38 25.15 25.25 22.15 22.25 35.50 35.90 25.15 25.25 22.15 22.25 30 50 80 100
p r e l i m i n a r y amd 63 am53c94/AM53C96 trademarks copyright ? 1993 advanced micro devices, all rights reserved. glitch eater is a trademark of advanced micro devices, inc. amd and am386 are registered trademarks of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

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